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Change enable_interrupts, disable_interrupts and clear_interrupts from Gpio0 to DeviceGpioPins
1 parent 365aba5 commit 42f9cfc

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3 files changed

+131
-145
lines changed

3 files changed

+131
-145
lines changed

‎e310x-hal/src/device.rs‎

Lines changed: 112 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
//! Device resources available in FE310-G000 and FE310-G002 chip packages
22
33
use crate::core::CorePeripherals;
4-
use crate::gpio::{gpio0::*, GpioExt, Unknown};
4+
use crate::gpio::{gpio0::*, EventType, GpioExt, Unknown};
55
use e310x::{
66
Aonclk, Backup, Gpio0, Otp, Peripherals, Pmu, Prci, Pwm0, Pwm1, Pwm2, Qspi0, Qspi1, Rtc, Uart0,
77
Wdog,
@@ -92,6 +92,117 @@ pub struct DeviceGpioPins {
9292
pub pin23: Pin23<Unknown>,
9393
}
9494

95+
impl DeviceGpioPins {
96+
/// Enables the specified interrupt event for all the GPIO pins.
97+
///
98+
/// # Note
99+
///
100+
/// This function does not enable the interrupts in the PLIC, it only sets the
101+
/// interrupt enable bits in the GPIO peripheral. You must call the
102+
/// [`enable_exti()`](super::gpio::gpio0::Pin0::enable_exti) method of every pin
103+
/// to enable their interrupt in the PLIC.
104+
pub fn enable_interrupts(&self, event: EventType) {
105+
let gpio = unsafe { Gpio0::steal() };
106+
107+
match event {
108+
EventType::High => {
109+
unsafe { gpio.high_ie().write(|w| w.bits(0xFFFFFFFF)) };
110+
}
111+
EventType::Low => {
112+
unsafe { gpio.low_ie().write(|w| w.bits(0xFFFFFFFF)) };
113+
}
114+
EventType::BothLevels => unsafe {
115+
gpio.high_ie().write(|w| w.bits(0xFFFFFFFF));
116+
gpio.low_ie().write(|w| w.bits(0xFFFFFFFF));
117+
},
118+
EventType::Rise => {
119+
unsafe { gpio.rise_ie().write(|w| w.bits(0xFFFFFFFF)) };
120+
}
121+
EventType::Fall => {
122+
unsafe { gpio.fall_ie().write(|w| w.bits(0xFFFFFFFF)) };
123+
}
124+
EventType::BothEdges => unsafe {
125+
gpio.rise_ie().write(|w| w.bits(0xFFFFFFFF));
126+
gpio.fall_ie().write(|w| w.bits(0xFFFFFFFF));
127+
},
128+
EventType::All => unsafe {
129+
gpio.high_ie().write(|w| w.bits(0xFFFFFFFF));
130+
gpio.low_ie().write(|w| w.bits(0xFFFFFFFF));
131+
gpio.rise_ie().write(|w| w.bits(0xFFFFFFFF));
132+
gpio.fall_ie().write(|w| w.bits(0xFFFFFFFF));
133+
},
134+
}
135+
}
136+
137+
/// Disables the specified interrupt event for all the GPIO pins.
138+
pub fn disable_interrupts(&self, event: EventType) {
139+
let gpio = unsafe { Gpio0::steal() };
140+
141+
match event {
142+
EventType::High => unsafe {
143+
gpio.high_ie().write(|w| w.bits(0x00000000));
144+
},
145+
EventType::Low => unsafe {
146+
gpio.low_ie().write(|w| w.bits(0x00000000));
147+
},
148+
EventType::BothLevels => unsafe {
149+
gpio.high_ie().write(|w| w.bits(0x00000000));
150+
gpio.low_ie().write(|w| w.bits(0x00000000));
151+
},
152+
EventType::Rise => unsafe {
153+
gpio.rise_ie().write(|w| w.bits(0x00000000));
154+
},
155+
EventType::Fall => unsafe {
156+
gpio.fall_ie().write(|w| w.bits(0x00000000));
157+
},
158+
EventType::BothEdges => unsafe {
159+
gpio.rise_ie().write(|w| w.bits(0x00000000));
160+
gpio.fall_ie().write(|w| w.bits(0x00000000));
161+
},
162+
EventType::All => unsafe {
163+
gpio.high_ie().write(|w| w.bits(0x00000000));
164+
gpio.low_ie().write(|w| w.bits(0x00000000));
165+
gpio.rise_ie().write(|w| w.bits(0x00000000));
166+
gpio.fall_ie().write(|w| w.bits(0x00000000));
167+
},
168+
}
169+
}
170+
171+
/// Clears the specified interrupt event pending flag for all the GPIO pins.
172+
pub fn clear_interrupts(&self, event: EventType) {
173+
let gpio = unsafe { Gpio0::steal() };
174+
175+
match event {
176+
EventType::High => unsafe {
177+
gpio.high_ip().write(|w| w.bits(0xFFFFFFFF));
178+
},
179+
EventType::Low => unsafe {
180+
gpio.low_ip().write(|w| w.bits(0xFFFFFFFF));
181+
},
182+
EventType::BothLevels => unsafe {
183+
gpio.high_ip().write(|w| w.bits(0xFFFFFFFF));
184+
gpio.low_ip().write(|w| w.bits(0xFFFFFFFF));
185+
},
186+
EventType::Rise => unsafe {
187+
gpio.rise_ip().write(|w| w.bits(0xFFFFFFFF));
188+
},
189+
EventType::Fall => unsafe {
190+
gpio.fall_ip().write(|w| w.bits(0xFFFFFFFF));
191+
},
192+
EventType::BothEdges => unsafe {
193+
gpio.rise_ip().write(|w| w.bits(0xFFFFFFFF));
194+
gpio.fall_ip().write(|w| w.bits(0xFFFFFFFF));
195+
},
196+
EventType::All => unsafe {
197+
gpio.high_ip().write(|w| w.bits(0xFFFFFFFF));
198+
gpio.low_ip().write(|w| w.bits(0xFFFFFFFF));
199+
gpio.rise_ip().write(|w| w.bits(0xFFFFFFFF));
200+
gpio.fall_ip().write(|w| w.bits(0xFFFFFFFF));
201+
},
202+
}
203+
}
204+
}
205+
95206
impl From<Gpio0> for DeviceGpioPins {
96207
fn from(gpio: Gpio0) -> Self {
97208
let parts = gpio.split();

‎e310x-hal/src/gpio.rs‎

Lines changed: 0 additions & 134 deletions
Original file line numberDiff line numberDiff line change
@@ -45,22 +45,6 @@ pub trait GpioExt {
4545

4646
/// Splits the GPIO block into independent pins and registers.
4747
fn split(self) -> Self::Parts;
48-
49-
/// Enables the specified interrupt event for all the GPIO pins.
50-
///
51-
/// # Note
52-
///
53-
/// This function does not enable the interrupts in the PLIC, it only sets the
54-
/// interrupt enable bits in the GPIO peripheral. You must call the
55-
/// [`enable_exti()`](super::gpio::gpio0::Pin0::enable_exti) method of every pin
56-
/// to enable their interrupt in the PLIC.
57-
fn enable_interrupts(event: EventType);
58-
59-
/// Disables the specified interrupt event for all the GPIO pins.
60-
fn disable_interrupts(event: EventType);
61-
62-
/// Clears the specified interrupt event pending flag for all the GPIO pins.
63-
fn clear_interrupts(event: EventType);
6448
}
6549

6650
/// Unknown mode (type state)
@@ -228,126 +212,8 @@ macro_rules! gpio {
228212
)+
229213
}
230214
}
231-
232-
fn enable_interrupts(event: EventType) {
233-
let p = Self::peripheral();
234-
235-
match event {
236-
EventType::High => {
237-
unsafe { p.high_ie().write(|w| w.bits(0xFFFFFFFF)) };
238-
}
239-
EventType::Low => {
240-
unsafe{ p.low_ie().write(|w| w.bits(0xFFFFFFFF)) };
241-
}
242-
EventType::BothLevels => {
243-
unsafe {
244-
p.high_ie().write(|w| w.bits(0xFFFFFFFF));
245-
p.low_ie().write(|w| w.bits(0xFFFFFFFF));
246-
}
247-
}
248-
EventType::Rise => {
249-
unsafe{ p.rise_ie().write(|w| w.bits(0xFFFFFFFF)) };
250-
}
251-
EventType::Fall => {
252-
unsafe{ p.fall_ie().write(|w| w.bits(0xFFFFFFFF)) };
253-
}
254-
EventType::BothEdges => {
255-
unsafe {
256-
p.rise_ie().write(|w| w.bits(0xFFFFFFFF));
257-
p.fall_ie().write(|w| w.bits(0xFFFFFFFF));
258-
}
259-
}
260-
EventType::All => {
261-
unsafe {
262-
p.high_ie().write(|w| w.bits(0xFFFFFFFF));
263-
p.low_ie().write(|w| w.bits(0xFFFFFFFF));
264-
p.rise_ie().write(|w| w.bits(0xFFFFFFFF));
265-
p.fall_ie().write(|w| w.bits(0xFFFFFFFF));
266-
}
267-
}
268-
}
269-
}
270-
271-
fn disable_interrupts(event: EventType) {
272-
let p = Self::peripheral();
273-
274-
match event {
275-
EventType::High => {
276-
unsafe { p.high_ie().write(|w| w.bits(0x00000000)); }
277-
}
278-
EventType::Low => {
279-
unsafe { p.low_ie().write(|w| w.bits(0x00000000)); }
280-
}
281-
EventType::BothLevels => {
282-
unsafe {
283-
p.high_ie().write(|w| w.bits(0x00000000));
284-
p.low_ie().write(|w| w.bits(0x00000000));
285-
}
286-
}
287-
EventType::Rise => {
288-
unsafe { p.rise_ie().write(|w| w.bits(0x00000000)); }
289-
}
290-
EventType::Fall => {
291-
unsafe { p.fall_ie().write(|w| w.bits(0x00000000)); }
292-
}
293-
EventType::BothEdges => {
294-
unsafe {
295-
p.rise_ie().write(|w| w.bits(0x00000000));
296-
p.fall_ie().write(|w| w.bits(0x00000000));
297-
}
298-
}
299-
EventType::All => {
300-
unsafe {
301-
p.high_ie().write(|w| w.bits(0x00000000));
302-
p.low_ie().write(|w| w.bits(0x00000000));
303-
p.rise_ie().write(|w| w.bits(0x00000000));
304-
p.fall_ie().write(|w| w.bits(0x00000000));
305-
}
306-
}
307-
}
308-
}
309-
310-
fn clear_interrupts(event: EventType) {
311-
let p = Self::peripheral();
312-
313-
match event {
314-
EventType::High => {
315-
unsafe { p.high_ip().write(|w| w.bits(0xFFFFFFFF)); }
316-
}
317-
EventType::Low => {
318-
unsafe { p.low_ip().write(|w| w.bits(0xFFFFFFFF)); }
319-
}
320-
EventType::BothLevels => {
321-
unsafe {
322-
p.high_ip().write(|w| w.bits(0xFFFFFFFF));
323-
p.low_ip().write(|w| w.bits(0xFFFFFFFF));
324-
}
325-
}
326-
EventType::Rise => {
327-
unsafe { p.rise_ip().write(|w| w.bits(0xFFFFFFFF)); }
328-
}
329-
EventType::Fall => {
330-
unsafe { p.fall_ip().write(|w| w.bits(0xFFFFFFFF)); }
331-
}
332-
EventType::BothEdges => {
333-
unsafe {
334-
p.rise_ip().write(|w| w.bits(0xFFFFFFFF));
335-
p.fall_ip().write(|w| w.bits(0xFFFFFFFF));
336-
}
337-
}
338-
EventType::All => {
339-
unsafe {
340-
p.high_ip().write(|w| w.bits(0xFFFFFFFF));
341-
p.low_ip().write(|w| w.bits(0xFFFFFFFF));
342-
p.rise_ip().write(|w| w.bits(0xFFFFFFFF));
343-
p.fall_ip().write(|w| w.bits(0xFFFFFFFF));
344-
}
345-
}
346-
}
347-
}
348215
}
349216

350-
351217
$(
352218
/// Pin
353219
pub struct $PXi<MODE> {

‎hifive1-examples/examples/button_interrupt.rs‎

Lines changed: 19 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,11 @@ use core::cell::RefCell;
66
use critical_section::Mutex;
77
use hifive1::{
88
clock,
9-
hal::{DeviceResources, gpio::{Input, PullUp, EventType, gpio0}, e310x::Gpio0, prelude::*},
9+
hal::{
10+
gpio::{gpio0, EventType, Input, PullUp},
11+
prelude::*,
12+
DeviceResources,
13+
},
1014
pin, sprintln, stdout, Led,
1115
};
1216
extern crate panic_halt;
@@ -21,12 +25,12 @@ fn gpio9_handler() {
2125
critical_section::with(|cs| {
2226
let button_ref = BUTTON.borrow_ref(cs);
2327
let button = button_ref.as_ref().unwrap();
24-
28+
2529
// Check the interrupt source
26-
if button.is_interrupt_pending(EventType::Rise){
30+
if button.is_interrupt_pending(EventType::Rise) {
2731
sprintln!("Rising Edge");
2832
}
29-
if button.is_interrupt_pending(EventType::Fall){
33+
if button.is_interrupt_pending(EventType::Fall) {
3034
sprintln!("Falling Edge");
3135
}
3236

@@ -45,6 +49,10 @@ fn main() -> ! {
4549
// Configure clocks
4650
let clocks = clock::configure(p.PRCI, p.AONCLK, 320.mhz().into());
4751

52+
// Disable and clear all GPIO interrupts
53+
pins.disable_interrupts(EventType::All);
54+
pins.clear_interrupts(EventType::All);
55+
4856
// Configure UART for stdout
4957
stdout::configure(
5058
p.UART0,
@@ -55,11 +63,7 @@ fn main() -> ! {
5563
);
5664

5765
sprintln!("Configuring GPIOs...");
58-
59-
// Disable and clear all GPIO interrupts
60-
Gpio0::disable_interrupts(EventType::All);
61-
Gpio0::clear_interrupts(EventType::All);
62-
66+
6367
// Configure button pin (GPIO9) as pull-up input
6468
let button = pins.pin9.into_pull_up_input();
6569
// Configure blue LED pin (GPIO21) as inverted output
@@ -96,7 +100,12 @@ fn main() -> ! {
96100
// Check if the button is low
97101
let mut button_state = false;
98102
critical_section::with(|cs| {
99-
button_state = BUTTON.borrow_ref_mut(cs).as_mut().unwrap().is_low().unwrap();
103+
button_state = BUTTON
104+
.borrow_ref_mut(cs)
105+
.as_mut()
106+
.unwrap()
107+
.is_low()
108+
.unwrap();
100109
});
101110

102111
if button_state {

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