Add sail implementation

[rez5427]

relate to #339

[sequencer]

Here are some of my concerns:

• How to define the architecture states, and the access API of them, they should have a concrete documentation or even implementation?(I personally prefer documentation).
• Not all architecture states are necessary for different extensions, so the problem becomes: how to define the architecture state for each extension firstly. And of cause please provide corresponding ABI for accessing each computer architecture states.
• CSR is tricky, maybe you need to add more CSR regfileds info to riscv-opcodes firstly.
• How to use it? Should a codegen-based emulator living in this repo? I don't this so, but it can be added for generating the pdf specifications.

Another point is we already have riscv/sail-riscv, and we should add these codes their. However from my point of view, that's only a concrete RISC-V software implementation, doesn't formally define the instruction and the architecture state, we need to have a sound definition of extensions and each instructions.

But after all, the repo is riscv-opcodes, which only defines the opcode for RISC-V, I personally like this, but anyway need to ask @aswaterman to decide should we add these sail implementation snippets here:)

[sequencer]

The branch and jal update the nextPC, why other instructions doesn't?