Add struct Board for MPS3-AN536
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Removes a bunch of duplicate code from the examples.
korken89
suggested changes
Oct 11, 2025
| #[cfg(feature = "gic")] | ||
| pub gic: arm_gic::gicv3::GicV3<'static>, | ||
| /// The Arm Virtual Generic Timer | ||
| pub vgt: cortex_ar::generic_timer::El1VirtualTimer, |
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| pub vgt: cortex_ar::generic_timer::El1VirtualTimer, | |
| pub vgt: cortex_ar::generic_timer::El1VirtualTimer, | |
| pub virtual_timer: cortex_ar::generic_timer::El1VirtualTimer, |
| /// The Arm Virtual Generic Timer | ||
| pub vgt: cortex_ar::generic_timer::El1VirtualTimer, | ||
| /// The Arm Physical Generic Timer | ||
| pub pgt: cortex_ar::generic_timer::El1PhysicalTimer, |
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| pub pgt: cortex_ar::generic_timer::El1PhysicalTimer, | |
| pub pgt: cortex_ar::generic_timer::El1PhysicalTimer, | |
| pub physical_timer: cortex_ar::generic_timer::El1PhysicalTimer, |
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korken89
suggested changes
Oct 11, 2025
| { | ||
| Some(Board { | ||
| #[cfg(feature = "gic")] | ||
| gic: unsafe { make_gic() }, |
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| gic: unsafe { make_gic() }, | |
| // SAFETY: This is the first and only call to `make_gic()` as guaranteed by | |
| // the atomic flag check above, ensuring no aliasing of GIC register access. | |
| gic: unsafe { make_gic() }, |
| Some(Board { | ||
| #[cfg(feature = "gic")] | ||
| gic: unsafe { make_gic() }, | ||
| vgt: unsafe { cortex_ar::generic_timer::El1VirtualTimer::new() }, |
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| vgt: unsafe { cortex_ar::generic_timer::El1VirtualTimer::new() }, | |
| // SAFETY: This is the first and only time we create the virtual timer instance | |
| // as guaranteed by the atomic flag check above, ensuring exclusive access. | |
| vgt: unsafe { cortex_ar::generic_timer::El1VirtualTimer::new() }, |
| #[cfg(feature = "gic")] | ||
| gic: unsafe { make_gic() }, | ||
| vgt: unsafe { cortex_ar::generic_timer::El1VirtualTimer::new() }, | ||
| pgt: unsafe { cortex_ar::generic_timer::El1PhysicalTimer::new() }, |
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| pgt: unsafe { cortex_ar::generic_timer::El1PhysicalTimer::new() }, | |
| // SAFETY: This is the first and only time we create the physical timer instance | |
| // as guaranteed by the atomic flag check above, ensuring exclusive access. | |
| pgt: unsafe { cortex_ar::generic_timer::El1PhysicalTimer::new() }, |
| gicd_base, | ||
| gicr_base | ||
| ); | ||
| let gicd = unsafe { |
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| let gicd = unsafe { | |
| // SAFETY: `gicd_base` points to the valid GICD MMIO region as obtained from the | |
| // hardware CBAR register. This pointer is used exclusively by this GIC instance. | |
| let gicd = unsafe { |
| arm_gic::UniqueMmioPointer::new(core::ptr::NonNull::new(gicd_base.cast()).unwrap()) | ||
| }; | ||
| let gicr_base = core::ptr::NonNull::new(gicr_base.cast()).unwrap(); | ||
| let mut gic = unsafe { arm_gic::gicv3::GicV3::new(gicd, gicr_base, 1, false) }; |
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| let mut gic = unsafe { arm_gic::gicv3::GicV3::new(gicd, gicr_base, 1, false) }; | |
| // SAFETY: The GICD and GICR base addresses point to valid GICv3 MMIO regions as | |
| // obtained from the hardware CBAR register. This function is only called once | |
| // (via Board::new()'s atomic guard), ensuring exclusive ownership of the GIC. | |
| let mut gic = unsafe { arm_gic::gicv3::GicV3::new(gicd, gicr_base, 1, false) }; |
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Holds all the hardware specific to the MPS3-AN536, making the examples simpler.