EE560: Reconfigurable Computing

Behavioral Simulation of Convolution of Image using a Kernel

Image-Processing-Inversion-

Behavioral Simulation of Convolution of Image using a Kernel

Image Processing - Image Inversion

This repository contains the implementation of an image inversion algorithm using Verilog. The image inversion process involves flipping the color values of the pixels in an image, resulting in a negative version of the original image. This can be particularly useful in various image processing applications and analysis.

Repository Structure

The repository includes the following files:

1. Verilog Files

   • top.v: The top-level module for the image inversion algorithm. It integrates all the other modules and defines the overall structure of the design.
   • tb.v: The testbench for verifying the functionality of the image inversion algorithm. It provides the necessary stimuli and checks the output against expected results.
   • controller.v: The controller module responsible for managing the data flow and control signals between the various components of the design.
   • cov_inversion.v: The core module that performs the actual image inversion. It processes the input image data and produces the inverted output.
   • rowbuffer.v: The row buffer module used for temporarily storing rows of image data during processing.

2. Image Files

   • Input image file(s): The original image(s) to be processed. These files should be in a compatible format that the Verilog modules can read.
   • Output image file(s): The resulting image(s) after the inversion process. These files will be generated by the simulation and stored for comparison with the input images.

How to Use

This repository contains the Verilog design and simulation files for performing a behavioral simulation of an image convolution using a kernel. The project uses FIFO and AXI streaming to process the image data. The design performs pixel inversion as part of the exercise.

Introduction

This project provides step-by-step instructions for performing a Verilog behavioral simulation on a BMP image. The required design source files perform the image pixel inversion using an inversion operation.

Step-by-Step Instructions

Step 1: Creating a Project

1. Create a new project in your preferred Verilog simulation tool.

Step 2: Uploading Design Files

1. Upload the provided Verilog design files to the project.

Step 3: Configuring FIFO using FIFO Generator

1. From the IP-Catalog (in Project Manager), search for FIFO Generator as shown in Figure 1, and double-click on the FIFO Generator to select it.
2. Change the component name to FIFO. Select the AXI Stream option.
3. Configure the AXI4-Stream ports by setting TDATA NUM BYTES to 1 and all other ports to 0, as illustrated in Figure 3.
4. Navigate to the Config menu, set the FIFO Depth to 16 (minimum), and configure the Data Threshold Parameters to `Single Programmable Full Threshold Constant.
5. Click OK, and when the pop-up window appears, select Generate to create the FIFO.

Step 4: Running the Simulation

1. Upload the provided testbench file tb.v to the project.
2. Go to the directory containing your project and navigate to the path: projectname.sim/sim1/behav/xsim/.
3. Place the input image.bmp file in this directory.
4. In Vivado, select Run Simulation → Run Behavioral Simulation.
5. After running the simulation, an output image.bmp will be generated and stored in the same directory.

Step 5: Verification Using Python

1. You can verify the output image using Python, which generates the expected output image.

2. The hardware implementation will produce an output image. You can compare both results for verification.

3. Check Output: After the simulation completes, check the generated output image file(s) and compare them with the input image to verify the inversion process.