AMD/Xilinx Versal Gen 1 VMK180 wolfBoot support

arch.mk

@@ -78,23 +78,34 @@ ifeq ($(ARCH),AARCH64)
       HASH_HAL=1
       CFLAGS+=-DWOLFBOOT_ZYNQMP_CSU
     endif
-  else
-    ifeq ($(TARGET),nxp_ls1028a)
-      ARCH_FLAGS=-mcpu=cortex-a72+crypto -march=armv8-a+crypto -mtune=cortex-a72
-      CFLAGS+=$(ARCH_FLAGS) -DCORTEX_A72
+  endif
 
-      CFLAGS +=-ffunction-sections -fdata-sections
-      LDFLAGS+=-Wl,--gc-sections
+  ifeq ($(TARGET),versal)
+    # AMD Versal ACAP (VMK180) - Dual Cortex-A72
+    ARCH_FLAGS=-mcpu=cortex-a72+crypto -march=armv8-a+crypto -mtune=cortex-a72
+    CFLAGS+=$(ARCH_FLAGS) -DCORTEX_A72
+    CFLAGS+=-DWOLFBOOT_DUALBOOT
+    # Support detection and skip of U-Boot legacy header
+    CFLAGS+=-DWOLFBOOT_UBOOT_LEGACY
+  endif
 
-      ifeq ($(DEBUG_UART),0)
-        CFLAGS+=-fno-builtin-printf
-      endif
+  ifeq ($(TARGET),nxp_ls1028a)
+    ARCH_FLAGS=-mcpu=cortex-a72+crypto -march=armv8-a+crypto -mtune=cortex-a72
+    CFLAGS+=$(ARCH_FLAGS) -DCORTEX_A72
 
-      SPI_TARGET=nxp
-    else
-      # By default disable ARM ASM for other targets
-      NO_ARM_ASM?=1
+    CFLAGS +=-ffunction-sections -fdata-sections
+    LDFLAGS+=-Wl,--gc-sections
+
+    ifeq ($(DEBUG_UART),0)
+      CFLAGS+=-fno-builtin-printf
     endif
+
+    SPI_TARGET=nxp
+  endif
+
+  # Default ARM ASM setting for unrecognized AARCH64 targets
+  ifeq ($(filter zynq versal nxp_ls1028a,$(TARGET)),)
+    NO_ARM_ASM?=1
   endif
 
   ifeq ($(SPMATH),1)

config/examples/versal_vmk180.config

@@ -0,0 +1,113 @@
+# wolfBoot configuration for AMD Versal VMK180 - DDR Boot (U-Boot Replacement)
+# Versal Prime VM1802 ACAP - Dual ARM Cortex-A72
+#
+# This configuration replaces U-Boot in the Versal boot flow:
+#   PLM -> PSM -> BL31 (EL3) -> wolfBoot (EL2) -> Linux (EL1)
+#
+# wolfBoot entry point is 0x8000000 in DDR, running at EL2 (non-secure)
+# All clock, MIO, and DDR initialization is done by PLM/PSM before wolfBoot starts
+
+ARCH?=AARCH64
+TARGET?=versal
+
+WOLFBOOT_VERSION?=1
+
+# ECC-384 with SHA-384 (good balance of security and performance)
+SIGN?=ECC384
+HASH?=SHA384
+IMAGE_HEADER_SIZE?=512
+
+# RSA 4096-bit with SHA3-384 (alternative)
+#SIGN?=RSA4096
+#HASH?=SHA3
+#IMAGE_HEADER_SIZE?=1024
+
+# Debug options
+DEBUG?=1
+DEBUG_SYMBOLS=1
+DEBUG_UART=1
+
+# Boot Benchmarking (optional):
+# Enables timing of boot operations (flash read, integrity, signature).
+BOOT_BENCHMARK?=1
+
+VTOR?=1
+CORTEX_M0?=0
+NO_ASM?=0
+ALLOW_DOWNGRADE?=0
+NVM_FLASH_WRITEONCE?=0
+V?=0
+SPMATH?=1
+RAM_CODE?=0
+DUALBANK_SWAP?=0
+PKA?=0
+WOLFTPM?=0
+
+# Flash configuration
+EXT_FLASH?=1
+NO_XIP=1
+
+# ELF loading support
+ELF?=1
+
+# Toolchain
+USE_GCC=1
+CROSS_COMPILE=aarch64-none-elf-
+
+# ============================================================================
+# Boot Memory Layout
+# ============================================================================
+# wolfBoot runs from DDR at 0x8000000 (same address as U-Boot)
+# This matches the partition header from PetaLinux BOOT.BIN:
+#   exec_addr: 0x08000000, load_addr: 0x08000000
+#   EL: el-2, trustzone: non-secure, aarch-64
+WOLFBOOT_ORIGIN=0x8000000
+
+# Optional debugging with OCRAM
+# Versal Gen 1 (VMK180): OCM is 256KB at 0xFFFC0000 - 0xFFFFFFFF
+# Versal Gen 2: OCM is 2MB at 0xFFE00000 - 0xFFFFFFFF
+#WOLFBOOT_ORIGIN=0xFFFC0000
+
+# Flash Sector Size (QSPI)
+WOLFBOOT_SECTOR_SIZE=0x20000
+
+# Application Partition Size (44MB)
+WOLFBOOT_PARTITION_SIZE=0x2C00000
+
+# Location in Flash for Primary Boot Partition
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x800000
+
+# Load Partition to RAM Address (Linux kernel loads here)
+WOLFBOOT_LOAD_ADDRESS?=0x10000000
+
+# Location in Flash for Secondary Partition (update image)
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x3400000
+
+# Location to store wolfBoot state/swap
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x6000000
+
+# DTS (Device Tree) - matches addresses from BOOT.BIN analysis
+WOLFBOOT_LOAD_DTS_ADDRESS?=0x1000
+WOLFBOOT_DTS_BOOT_ADDRESS?=0x7B0000
+WOLFBOOT_DTS_UPDATE_ADDRESS?=0x39B0000
+
+# Speed up reads by using larger blocks
+CFLAGS_EXTRA+=-DWOLFBOOT_SHA_BLOCK_SIZE=4096
+
+# UART Configuration - UART0 for APU console
+CFLAGS_EXTRA+=-DDEBUG_UART_NUM=0
+
+# QSPI Reference Clock: Ref (300MHz default for Versal)
+#CFLAGS_EXTRA+=-DGQSPI_CLK_REF=300000000
+
+# QSPI Bus Divisor: (2 << div) = BUS (0=div2, 1=div4, 2=div8)
+# MT25QU01G max: 133MHz Quad Read (0x6C) with 8 dummy cycles
+# div=0: 300MHz/2 = 150MHz (above spec but tested working)
+# div=1: 300MHz/4 = 75MHz (within spec, default)
+# div=2: 300MHz/8 = 37.5MHz (conservative)
+#CFLAGS_EXTRA+=-DGQSPI_CLK_DIV=1
+
+# QSPI flash options (uncomment to enable)
+#CFLAGS_EXTRA+=-DDEBUG_QSPI       # Enable QSPI debug logging
+#CFLAGS_EXTRA+=-DGQSPI_MODE_IO    # Use polling instead of DMA (slower)
+#CFLAGS_EXTRA+=-DTEST_EXT_FLASH   # Run flash erase/write/read test

docs/Targets.md

@@ -48,6 +48,7 @@ This README describes configuration of supported targets.
 * [TI Hercules TMS570LC435](#ti-hercules-tms570lc435)
 * [Vorago VA416x0](#vorago-va416x0)
 * [Xilinx Zynq UltraScale](#xilinx-zynq-ultrascale)
+* [Versal Gen 1 VMK180](#versal-gen-1-vmk180)
 
 ## STM32F4
 
@@ -1859,6 +1860,165 @@ qemu-system-aarch64 -machine xlnx-zcu102 -cpu cortex-a53 -serial stdio -display
 `tools/keytools/sign --rsa4096 --sha3 /srv/linux-rpi4/vmlinux.bin wolfboot_signing_private_key.der 1`
 
 
+## Versal Gen 1 VMK180
+
+AMD Versal Prime Series VMK180 Evaluation Kit - Versal Prime XCVM1802-2MSEVSVA2197 Adaptive SoC - Dual ARM Cortex-A72
+
+wolfBoot replaces U-Boot in the Versal boot flow:
+```
+PLM -> PSM -> BL31 (EL3) -> wolfBoot (EL2) -> Linux (EL1)
+```
+
+wolfBoot runs from DDR at address `0x8000000` at EL2 (non-secure). All clock, MIO, and DDR initialization is handled by PLM/PSM before wolfBoot starts.
+
+See example configuration file at `config/examples/versal_vmk180.config`.
+
+### Prerequisites
+
+1. **Xilinx Vitis 2024.1 or 2024.2** (required for bootgen - 2025.1 or later has QSPI boot issues)
+   - Set `VITIS_PATH` environment variable: `export VITIS_PATH=/opt/Xilinx/Vitis/2024.1`
+
+2. **Toolchain**
+   - ARM GCC toolchain: `aarch64-none-elf-gcc`
+
+
+### Configuration Options
+
+Key configuration options in `config/examples/versal_vmk180.config`:
+
+- `ARCH=AARCH64` - ARM 64-bit architecture
+- `TARGET=versal` - Versal platform target
+- `WOLFBOOT_ORIGIN=0x8000000` - Entry point in DDR
+- `WOLFBOOT_SECTOR_SIZE=0x20000` - QSPI flash sector size (128KB)
+- `WOLFBOOT_PARTITION_SIZE=0x2C00000` - Application partition size (44MB)
+- `EXT_FLASH=1` - External flash support
+- `ELF=1` - ELF loading support
+
+### Memory Layout
+
+| Partition   | Size   | Address | Description |
+|-------------|--------|---------|-------------|
+| Bootloader  | -      | 0x8000000 | wolfBoot in DDR (loaded by BL31) |
+| Primary     | 44MB   | 0x800000 | Boot partition in QSPI |
+| Update      | 44MB   | 0x3400000 | Update partition in QSPI |
+| Swap        | -      | 0x6000000 | Swap area in QSPI |
+
+### Debugging
+
+For debugging with OCRAM (OCM), set `WOLFBOOT_ORIGIN=0xFFFC0000` in the config file. Versal Gen 1 OCM is 256KB at `0xFFFC0000 - 0xFFFFFFFF`.
+
+### Building wolfBoot
+
+Build wolfBoot from the wolfBoot root directory:
+
+```sh
+cp config/examples/versal_vmk180.config .config
+make clean
+make
+```
+
+### Building BOOT.BIN
+
+If you don't already have prebuilt firmware, clone the Xilinx prebuilt firmware repository:
+
+```sh
+git clone --branch xlnx_rel_v2024.1 https://github.com/Xilinx/soc-prebuilt-firmware.git
+export PREBUILT_DIR=$(pwd)/../soc-prebuilt-firmware/vmk180-versal
+```
+
+Copy the required files into wolfboot root directory:
+
+```sh
+cp ${PREBUILT_DIR}/project_1.pdi .
+cp ${PREBUILT_DIR}/plm.elf .
+cp ${PREBUILT_DIR}/psmfw.elf .
+cp ${PREBUILT_DIR}/bl31.elf .
+cp ${PREBUILT_DIR}/system-default.dtb .
+```
+
+Source the Vitis environment and generate BOOT.BIN using bootgen:
+
+```sh
+source ${VITIS_PATH}/settings64.sh
+bootgen -arch versal -image ./tools/scripts/vmk180/boot_wolfboot.bif -w -o BOOT.BIN
+```
+
+The BIF file (`boot_wolfboot.bif`) references files using relative paths in the same directory. After successful generation, `BOOT.BIN` will be created in `tools/scripts/vmk180/`.
+
+### Flashing QSPI
+
+Flash `BOOT.BIN` to QSPI flash using one of the following methods:
+
+- **Vitis**: Use the Hardware Manager to program the QSPI flash via JTAG. Load `BOOT.BIN` and program to QSPI32 flash memory.
+
+- **Lauterbach**: Use Trace32 to program QSPI flash via JTAG. Load `BOOT.BIN` and write to QSPI flash memory addresses.
+
+- **U-Boot via SD Card**: Boot from SD card with U-Boot, then use TFTP to download `BOOT.BIN` and program QSPI flash:
+  ```sh
+  tftp ${loadaddr} BOOT.BIN
+  sf probe 0 0 0
+  sf erase 0 +${filesize}
+  sf write ${loadaddr} 0 ${filesize}
+  ```
+
+### QSPI Flash
+
+VMK180 uses dual parallel MT25QU01GBBB flash (128MB each, 256MB total). The QSPI driver supports:
+- DMA mode (default) or IO polling mode (`GQSPI_MODE_IO`)
+- Quad SPI (4-bit) for faster reads
+- 4-byte addressing for full flash access
+- Hardware striping for dual parallel operation
+- 75MHz default clock (configurable via `GQSPI_CLK_DIV`)
+
+### Building and Signing Test Application
+
+```sh
+# Build and sign the test application
+make test-app/image.bin
+make test-app/image_v1_signed.bin
+```
+
+The signed test application will be at `test-app/image_v1_signed.bin`.
+
+### Flashing Test Application
+
+After flashing `BOOT.BIN` to QSPI offset 0x0, flash the signed test app to the boot partition at offset `0x800000` using your preferred method.
+
+### Example Boot Output
+
+```
+========================================
+wolfBoot Secure Boot - AMD Versal
+========================================
+Current EL: 2
+Timer Freq: 99999904 Hz
+QSPI: Lower ID: 20 BB 21
+QSPI: Upper ID: 20 BB 21
+QSPI: 75MHz, Quad mode, DMA
+Versions: Boot 1, Update 0
+Trying Boot partition at 0x800000
+Loading header 512 bytes from 0x800000 to 0xFFFFE00
+Loading image 664 bytes from 0x800200 to 0x10000000...done
+Boot partition: 0xFFFFE00 (sz 664, ver 0x1, type 0x601)
+Checking integrity...done
+Verifying signature...done
+Successfully selected image in part: 0
+Firmware Valid
+Loading elf at 0x10000000
+Invalid elf, falling back to raw binary
+Loading DTB (size 24894) from 0x1000 to RAM at 0x1000
+Booting at 0x10000000
+
+===========================================
+ wolfBoot Test Application - AMD Versal
+===========================================
+
+Application running successfully!
+
+Entering idle loop...
+```
+
+
 ## Cypress PSoC-6
 
 The Cypress PSoC 62S2 is a dual-core Cortex-M4 & Cortex-M0+ MCU. The secure boot process is managed by the M0+.