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PLD Configuration

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David Ryskalczyk edited this page Dec 9, 2021 · 4 revisions

PLD Structure

PLD 12C4 Structure

Source: PSoC 5LP Architecture TRM: Figure 21-2. PLD 12C4 Structure

PLD Configuration Registers

Address 0x00 0x01 0x02 0x03
0x00 PLD0_IT0C PLD1_IT0C PLD0_IT0T PLD1_IT0T
0x04 PLD0_IT1C PLD1_IT1C PLD0_IT1T PLD1_IT1T
0x08 PLD0_IT2C PLD1_IT2C PLD0_IT2T PLD1_IT2T
0x0C PLD0_IT3C PLD1_IT3C PLD0_IT3T PLD1_IT3T
0x10 PLD0_IT4C PLD1_IT4C PLD0_IT4T PLD1_IT4T
0x14 PLD0_IT5C PLD1_IT5C PLD0_IT5T PLD1_IT5T
0x18 PLD0_IT6C PLD1_IT6C PLD0_IT6T PLD1_IT6T
0x1C PLD0_IT7C PLD1_IT7C PLD0_IT7T PLD1_IT7T
0x20 PLD0_IT8C PLD1_IT8C PLD0_IT8T PLD1_IT8T
0x24 PLD0_IT9C PLD1_IT9C PLD0_IT9T PLD1_IT9T
0x28 PLD0_IT10C PLD1_IT10C PLD0_IT10T PLD1_IT10T
0x2C PLD0_IT11C PLD1_IT11C PLD0_IT11T PLD1_IT11T
0x30 PLD0_ORT0_PT PLD1_ORT0_PT PLD0_ORT1_PT PLD1_ORT1_PT
0x34 PLD0_ORT2_PT PLD1_ORT2_PT PLD0_ORT3_PT PLD1_ORT3_PT
0x38 PLD0_MC_CEN_CONST PLD1_MC_CEN_CONST PLD0_MC_XORFB PLD1_MC_XORFB
0x3C PLD0_MC_SET_RESET PLD1_MC_SET_RESET PLD0_MC_BYPASS PLD1_MC_BYPASS

These register addresses are from the PSoC 5LP Registers TRM.

Input Term Configuration

The input term registers (0x00 through 0x2F) are named in the style PLDx_ITyz, where x identifies the PLD in the UDB ([0..1]), y is the input term number ([0..11]), and z is either T for the True input term or C for the Complement input term. Each register is 8 bits wide and the bit number corresponds to the product term number (there are 8 product terms per PLD).

OR Term Configuration

The OR term registers (0x30 through 0x37) are named in the style PLDx_ORy_PT, where x identifies the PLD in the UDB ([0..1]) and y is the OR term number ([0..3]). Each register is 8 bits wide and the bit number corresponds to the product term number (there are 8 product terms per PLD).

Macrocell Configuration

The macrocell registers (0x38 through 0x3F) are named in the style PLDx_MC_y, where x identifies the PLD in the UDB ([0..1]) and y refers to the variable the register configures.

Macrocell Architecture

Macrocell Architecture

Source: PSoC 5LP Architecture TRM: Figure 21-3. Macrocell Architecture

Register Map

The following information comes from the Registers TRM.

  • COEN and CONST are controlled by the B[0..3]_P[0..7]_U[0..1]_MC_CFG_CEN_CONST registers.
  • XORFB[1:0] is controlled by the B[0..3]_P[0..7]_U[0..1]_MC_CFG_XORFB registers.
  • RSEL and SSEL are controlled by the B[0..3]_P[0..7]_U[0..1]_MC_CFG_SET_RESET registers.
  • BYP is controlled by the B[0..3]_P[0..7]_U[0..1]_MC_CFG_BYPASS registers.
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