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[AArch64] Remove post-decoding instruction mutations #156364
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[AArch64] Remove post-decoding instruction mutations #156364
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✅ With the latest revision this PR passed the C/C++ code formatter. |
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gentle ping |
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I'm not the biggest expert here, and bits<0> seems a little unusual, but as far as I can tell this LGTM. Thanks
It kind of makes sense if you look at related instructions, e.g.:
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These instructions can now be fully decoded automatically.
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This was updated in #156364 but `-ignore-non-decodable-operands` was removed from the wrong tablegen arg list (arm vs aarch64)
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/18/builds/21322 Here is the relevant piece of the build log for the reference
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/168/builds/16243 Here is the relevant piece of the build log for the reference
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/72/builds/15142 Here is the relevant piece of the build log for the reference
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Add
bits<0>
fields to instructions using the ZTR/MPR/MPR8 register classes.These register classes contain only one register, and it is not encoded in the instruction.
This way, the generated decoder can completely decode instructions without having to perform a post-decoding pass to insert missing operands.
Some immediate operands are also not encoded and have only one possible value "zero". Use this trick for them, too.
Finally, remove
-ignore-non-decodable-operands
option fromllvm-tblgen
invocation to ensure that non-decodable operands do not appear in the future.