[ARM] Remove most post-decoding instruction adjustments #156540
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This was referenced Sep 2, 2025
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This change adds basic `MCInst` verification (checks the number of operands) and fixes detected bugs. * `RFE*` instructions have only one operand, but `DecodeRFEInstruction` added two. * `DecodeMVEModImmInstruction` and `DecodeMVEVCMP` added a `vpred` operand, but this is what `AddThumbPredicate` normally does. This resulted in an extra `vpred` operand. * `DecodeMVEVADCInstruction` added an extra immediate operand. * `getARMInstruction` added a `pred` operand to instructions that don't have one (via `DecodePredicateOperand`). * `AddThumb1SBit` appended an extra register operand to instructions that don't modify CPSR (such as `tBL`). * Instructions in `NEONDup` namespace have `pred` operand that the generated code successfully decodes. The operand was added once again by `getARMInstruction`/`getThumbInstruction` via `AddThumbPredicate`. Functional changes extracted from #156540.
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✅ With the latest revision this PR passed the C/C++ code formatter. |
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The operand can be decoded automatically, without the need for post-decoding instruction modification. Part of #156540.
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Make the operands auto-decodable by adding `bits<0>` fields to instructions. Now we try to decode a vpred_n/vpred_r operand only if the instruction being decoded has one. We still need post-decoding pass to check/advance VPT state. Part of #156540.
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