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4 changes: 4 additions & 0 deletions riscv/CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- CSR helper macro `write_composite_csr` for writing 64-bit CSRs on 32-bit targets.
- Write utilities for `mcycle`, `minstret`

### Changed

- Simplify `riscv::interrupt::machine::nested`

## [v0.13.0] - 2025-02-18

### Added
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6 changes: 2 additions & 4 deletions riscv/src/interrupt/machine.rs
Original file line number Diff line number Diff line change
Expand Up @@ -192,12 +192,10 @@ where
}

// Restore MSTATUS.PIE, MSTATUS.MPP, and SEPC
let mut after_mstatus = mstatus::read();
if mstatus.mpie() {
after_mstatus.set_mpie(mstatus.mpie());
mstatus::set_mpie();
}
after_mstatus.set_mpp(mstatus.mpp());
mstatus::write(after_mstatus);
mstatus::set_mpp(mstatus.mpp());
mepc::write(mepc);

r
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